Decreasing device size and increasing device density has traditionally been a high priority for the manufacturing of integrated circuits. Optical lithography has been the driving force for device scaling. Conventional optical lithography is limited to about 80 nm pitch for single exposure patterning. While double and other multi-patterning processes can realize smaller pitch, these approaches are expensive and more complex.
Directed self-assembly (DSA), a technique which aligns self-assembling polymeric materials on a lithographically defined guide pattern, is a potential option for extending current optical lithography beyond its pitch and resolution limits. The self-assembling materials, for example, are block copolymers (BCPs) that consist of “A” homopolymer covalently attached to “B” homopolymer, which are coated over a lithographically defined guide pattern on a semiconductor substrate. The lithographically defined guide pattern is a pre-pattern that is encoded with spatial chemical and/or topographical information and serves to direct the self-assembly process and the pattern formed by the self-assembling materials. Subsequently, by annealing the DSA polymers, the A polymer chains and the B polymer chains undergo phase separation to form an A polymer region and a B polymer region that are registered to the guide pattern. Then, by removing either the A polymer region or the B polymer region by wet chemical or plasma-etch techniques, a mask is formed for transferring the nanopattern to the underlying substrate.
One DSA technique is graphoepitaxy in which self-assembly is directed by topographical features that are formed overlying a semiconductor substrate. This technique is used, for example, to create contact holes or vias that can be subsequently filled with conductive material for forming electrical connections between one or more layers of the semiconductor substrate. In particular, the topographical features are formed overlying the semiconductor substrate using a photomask that defines mask features and conventional lithographic techniques to transfer the mask features to a photoresist layer that overlies the semiconductor substrate to form a patterned photoresist layer. The pattern photoresist layer is then selectively etched to form the topographical features that define confinement wells. The confinement wells are filled with a BCP that is subsequently phase separated to form, for example, etchable cylinders or other etchable features that are each formed of either the A polymer region or the B polymer region of the BCP. The etchable cylinders are removed to form openings and define a mask for etch transferring the openings to the underlying semiconductor substrate.
Unfortunately, current techniques for forming DSA patterns can have considerable process variations that reduce the DSA process window (DSAPW). The DSAPW is defined as the total process variation for creating the DSA patterns including any process variations from lithographically transferring the mask features from a photomask to etch transferring the DSA pattern to the underlying semiconductor substrate. One approach to improving the DSAPW is to improve the lithographic process window for transferring the mask features from the photomask to the photoresist layer. In conventional lithography, non-printing lithographic assist features may be arranged on a photomask about a main feature that is intended to be transferred to the photoresist layer. These non-printing lithographic assist features help improve the process window by reducing the sensitivity to lithographic process variations, such as variations of dose and focus. The size of these non-printing lithographic assist features is relatively small such that they do not print or transfer to the photoresist layer and otherwise produce unintended features being subsequently formed in the integrated circuit. Unfortunately, the relatively small size of these non-printing lithographic assist features limits their benefit to improving the lithographic process window.
Accordingly, it is desirable to provide methods for fabricating integrated circuits with an improved process window for directed self-assembly. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.